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TCE: Input fifo not empty after reset

Written: Dec 4, 1996 - DW

When going from High TM rate back to low rate this message appeared.

This occurs when TCE has a problem on the comm link between OBE and TCE.

1. TCE wants to send a message to OBE
2. It checks to see if the fifo from OBE to TCE is empty so that a reply is 
3. It finds that is not empty so it resets it.
4. After the reset it checks the fifo status bit, the status bit says the fifo is not empty 
and this error message is sent.

This is probably because OBE was so late in answering the last TCE status 
request that TCE timed out and forgot about it, while OBE did not.

This probably means that one TCE status request got lost by OBE while packet acq 
by the spacecraft was turned off.  Here's what happened:

1. TCE requests status during high rate
2. OBE sets a flag so the status request gets filled at the next SCI packet acq.
3. Spacecraft turns off SCI packet acq
4. Flex rate -> IDLE
5. Flex rate -> LOW
6. SCI Packet Acq
7. OBE answers TCE status request at next SCI packet acq but TCE timed out a while ago
8. TCE now has another message it wants to send to OBE but finds an OBE message
waiting for it.

The fifo is reset but the fifo status bit does not show a clear fifo. 

I think the fifo probably does clear since later messages to get through but 
that the status bit perhaps doesn't reflect the change immediately.

Summary: Not serious, OBE has no idea of the timing of when packet acq is turned on or off.  
If we can do the packet acq off/on before TCE times out then this message should go 
away. (Not likely since Packet Acq is under the control of the spacecraft.)

One fix to try would be to add a delay before checking the fifo status bit.

Naval Research Lab - Code 7660 - DW